With respect to recent cellular phone units, attention has been given to a digital interface between BBLSI (Base Band Large Scale Integrated circuit, also referred to as baseband IC) and RFIC (Radio Frequency Integrated Circuit).
The standard DigRF v3, one of standards for digital serial interface between BBLSI and RFIC, is standardized by a group called DigRF Working Group in an organization named as MIPI (Mobile Industry Processor Interface Alliance). This standard is for such applications as GSM, EDGE, WCDMA, and the like. GSM is an abbreviation for Global System for Mobile Communication; EDGE is an abbreviation for Enhanced Data for GSM Evolution or Enhanced Data for GPRS; and WCDMA is an abbreviation for Wideband Code Division Multiple Access.
According to the standard DigRF v3, RFIC and BBLSI convert the differential analog signals of their respective interfaces into single ended digital signals. Interfaces for transmit data and reception data reduce electricity consumption and unwanted emission by a low-swing controlled-impedance differential pair and provide reliable data transfer at a high data rate. The peak-to-peak differential voltage is 0.9 V and the minimum differential voltage is 100 mV. The line driver and the line receiver of interfaces for transmit data and reception data are provided with sleep mode for power saving and brought into sleep mode during an interframe gap longer than a frame period. For transition to sleep mode, a line driver asserts a high level of “1” during a bit period immediately after the last bit of a frame. Thereafter, the line driver shifts to a low-power state in which it is kept at common mode voltage obtained by reducing the difference voltage of the interface to −5 mV to +20 mV. The hysteresis of the line receiver makes sure the display of a high level of “1” to the internal circuit of a receiver IC. To exit from sleep mode, the line driver drives a low level during at least an 8-bit period (for high-speed clock) or a 1-bit period (for low-speed or medium-speed clock) before the start of the initial bit in the synchronization sequence of a new frame.
According to the standard DigRF v3, further, the following is required to generate 312-MHz data clock used in when the reception data interface and the transmit data interface are in high speed mode: a high-speed interface clock generator is required both in RFIC and in the baseband LSI.
According to the standard DigRF v3, furthermore, transmitted transmit data and reception data are divided into multiple frames and each frame contains three fields, synchronization, header, and payload. The synchronization field contains a synchronization pattern of a predetermined 16-bit code “1010100001001011” and is used to allow the receiving side of a link to select a phase of clock appropriate to sample input data. The header field is comprised of eight bits and contains information on size, the logical channel type of each frame, a signal bit having different functions in the direction of transmit data and in the direction of reception data. The payload field is provided with seven different data sizes, 8 bit, 32 bit, 64 bit, 96 bit, 128 bit, 256 bit, and 512 bit.
Non-patent Document 1 listed below describes a high-speed digital interface configured by incorporating an A-D converter and a D-A converter in the RFIC of a cellular phone. Thus a digital signal generated at an RF transceiver chip is transferred to a baseband chip without causing degradation in an RF signal due to EMC (Electromagnetic Emission) or spikes in power supply voltage. This high-speed digital interface is comprised of: a pair of transmission lines; a differential driver for driving the pair of transmission lines; and a differential receiver for detecting the difference voltage of the pair of transmission lines. The differential driver is comprised of a differential push-pull and a current source coupled between this differential push-pull and power supply voltage. The differential receiver is comprised of a passive terminating resistor of 100Ω, a comparator with hysteresis, and a CMOS push-pull driver. This transmission is designated as R-LVDS (Reduced-Low-Voltage-Differential-Signaling) by the authors.    [Non-patent Document 1] K. Chabrak et al, “Design of a High-Speed Low-Power Digital Interface for Multi-Standard Mobile Transceiver RFIC's in 0.13 μm CMOS,” 2005 The European Conference on Wireless Technology, 3-4 Oct. 2005, PP. 217-220.